ARM Cortex-A76 Core Technical Reference Manual page 304

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Configurations
100798_0300_00_en
Reserved, .
RES0
Uncontainable error generation enable. The possible values are:
No uncontainable error is generated.
0
An uncontainable error might be generated when the Error Generation Counter is
1
triggered.
Reserved, .
RES0
There are no configuration notes.
ERR0PFGCTLR resets to
ERR0PFGCTLR is accessible from the following registers when ERRSELR.SEL==0:
• B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
on page B2-204.
Copyright © 2016–2018 Arm Limited or its affiliates. All rights
B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register
.
0x00000000
reserved.
Non-Confidential
B3 Error system registers
B3-304