ARM Cortex-A76 Core Technical Reference Manual page 454

D, [3]
C, [2]
P, [1]
E, [0]
Configurations
Bit fields and details that are not provided in this description are architecturally defined. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile.
100798_0300_00_en
Export of events is disabled. This is the reset value.
0
Export of events is enabled.
1
This bit is read/write and does not affect the generation of Performance Monitors interrupts on
the nPMUIRQ pin.
Clock divider:
When enabled, PMCCNTR_EL0 counts every clock cycle. This is the reset value.
0
When enabled, PMCCNTR_EL0 counts every 64 clock cycles.
1
This bit is read/write.
Clock counter reset. This bit is WO. The effects of writing to this bit are:
No action. This is the reset value.
0
Reset PMCCNTR_EL0 to 0.
1
This bit is always RAZ.
Resetting PMCCNTR_EL0 does not clear the PMCCNTR_EL0 overflow bit to 0. See the Arm
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
Event counter reset. This bit is WO. The effects of writing to this bit are:
No action. This is the reset value.
0
Reset all event counters, not including PMCCNTR_EL0, to zero.
1
This bit is always RAZ.
In Non-secure EL0 and EL1, a write of 1 to this bit does not reset event counters that
MDCR_EL2.HPMN reserves for EL2 use.
In EL2 and EL3, a write of 1 to this bit resets all the event counters.
Resetting the event counters does not clear any overflow bits to 0.
Enable. The possible values of this bit are:
All counters, including PMCCNTR_EL0, are disabled. This is the reset value.
0
All counters are enabled.
1
This bit is RW.
In Non-secure EL0 and EL1, this bit does not affect the operation of event counters that
MDCR_EL2.HPMN reserves for EL2 use.
On Warm reset, the field resets to 0.
AArch64 System register PMCR_EL0 is architecturally mapped to AArch32 System register
PMCR.
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D5.4 PMCR_EL0, Performance Monitors Control Register, EL0
reserved.
Non-Confidential
D5 AArch64 PMU registers
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D5-454