ARM Cortex-A76 Core Technical Reference Manual page 488

D8 AArch64 AMU registers
D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0
Traps and enables
If ACTLR_EL2.AMEN is 0, then Non-secure accesses to this register from EL0 and EL1 are
trapped to EL2.
If ACTLR_EL3.AMEN is 0, then accesses to this register from EL0, EL1, and EL2 are trapped
to EL3.
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