B4.2 Aarch64 Physical Gic Cpu Interface System Register Summary - ARM Cortex-A76 Core Technical Reference Manual

B4.2 AArch64 physical GIC CPU interface system register summary
The following table lists the AArch64 physical GIC CPU interface system registers that have
IMPLEMENTATION DEFINED
See the Arm
complete list of AArch64 physical GIC CPU interface system registers.
Name Op0 Op1 CRn CRm Op2 Type Description
ICC_AP0R0_EL1 3 0
ICC_AP1R0_EL1 3 0
ICC_BPR0_EL1 3 0
ICC_BPR1_EL1 3 0
ICC_CTLR_EL1 3 0
ICC_CTLR_EL3 3 6
ICC_SRE_EL1 3 0
ICC_SRE_EL2 3 4
ICC_SRE_EL3 3 6
100798_0300_00_en
bits.
Generic Interrupt Controller Architecture Specification for more information and a
®
Table B4-2 AArch64 physical GIC CPU interface system register summary
12 8 4 RW
12 9 0 RW
12 8 3 RW
12 12 3 RW
12 12 4 RW
12 12 4 RW
12 12 5 RW
12 9 5 RW
12 12 5 RW
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B4.2 AArch64 physical GIC CPU interface system register summary

B4.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0
Register 0, EL1 on page B4-315
B4.4 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1
Register 0 EL1 on page B4-316
B4.5 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0,
EL1 on page B4-317
B4.6 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1,
EL1 on page B4-318
B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
on page B4-319
B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3
on page B4-321
B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable
Register, EL1 on page B4-323
B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable
register, EL2 on page B4-324
B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable
register, EL3 on page B4-326
reserved.
B4 GIC registers
B4-314