B3.9 Err0Pfgfr, Error Pseudo Fault Generation Feature Register - ARM Cortex-A76 Core Technical Reference Manual

B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register
The ERR0PFGFR is the Cortex-A76 node register that defines which fault generation features are
implemented.
Bit field descriptions
ERR0PFGFR is a 32-bit register and is RO.
PFG, [31]
R, [30]
[29:7]
CE, [6]
DE, [5]
UEO, [4]
UER, [3]
UEU, [2]
100798_0300_00_en
31 30 29
R
PFG
0
RES
Pseudo Fault Generation. The value is:
The node implements a fault injection mechanism.
1
Restartable bit. When it reaches zero, the Error Generation Counter restarts from the
ERR0PFGCDN value or stops. The value is:
This feature is controllable.
1
Reserved.
RES0
Corrected Error generation. The value is:
This feature is controllable.
1
Deferred Error generation. The value is:
This feature is controllable.
1
Latent or Restartable Error generation. The value is:
The node does not support this feature.
0
Signaled or Recoverable Error generation. The value is:
The node does not support this feature.
0
Unrecoverable Error generation. The value is:
The node does not support this feature.
0
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B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register

Figure B3-7 ERR0PFGFR bit assignments
reserved.
Non-Confidential
B3 Error system registers
7 6 5 4 3 2 1 0
CE
DE
UEO
UER
UEU
UC
B3-305