Control Status Register (Fmcs) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 26 2M BIT FLASH MEMORY

26.3 Control Status Register (FMCS)

The control status register (FMCS) is used for write/erase operations on flash memory
via the registers in the flash memory interface circuit.
I Control status register (FMCS)
The diagram below shows the bit configuration of the control status register (FMCS).
Bit number
Address: 0000AE
Read/write
Initial value
The bits in the control status register (FMCS) have the following functions.
[Bit 7] INTE: INTerrupt Enable
This bit is used to generate an interrupt to the CPU due to the end of a flash memory write/
erase access.
If the INTE bit is set to "1" and the RDYINT bit is set to "1", an interrupt is issued to the CPU.
If the INTE bit is set to "0", no interrupt is issued.
0
1
[Bit 6] RDYINT: ReaDY INTerrupt
This bit is used to indicate the operation state of the flash memory.
At the end of a flash memory write/erase operation, this bit is normally set to "1". When this
bit remains "0" after the end of a flash memory write/erase operation, further flash memory
write/erase operations are not allowed. Only after this bit has been set to "1" at the end of a
write/erase operations is the next write/erase operation for flash memory allowed.
This bit is cleared by writing "0". Writing "1" has no effect. This bit is set to "1" according to
the end timing of the flash memory automatic algorithm (Refer to Section 26.4 "Method for
Starting the Flash Memory's Automatic Algorithm"). Read-modify-write (RMW) instructions
always return "1" for this bit.
0
1
472
7 6
INTE RDYINT WE
H
(R/W) (R/W) (R/W)
(0) (0) (0)
Interrupt at the end of write/erase operations prohibited
Interrupt at the end of write/erase operations allowed
Write/erase operation in progress
End of write/erase operation end (interrupt request generation)
5 4 3 2
RDY Reserved LPM1 Reserved LPM0
(W) (W) (R/W)
(X) (0) (0)
1 0
(W) (R/W)
(0) (0)