Flash Control Register (Fmcs) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual
16-bit microcontrollers
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Also See for F2MC-16LX MB90580 Series:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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C.3 Flash Control Register (FMCS)
Flash control register (FMCS) is a register which is used during programming or erasing the flash memory.
Flash Control Register (FMCS)
Address: 0000AE
Read/write
Initial value
[bit 7] INTE (INTerrupt Enable)
This bit is used to enable an interrupt to the CPU when the operation of programming/erasing the flash
memory is completed. An interrupt to the CPU will be generated when the INTE bit is "1" and the RDYINT
bit is a "1". When the INTE bit is "0", an interrupt will not be generated.
INTE
0
1
[bit 6] RDYINT (ReaDY INTerrupt)
This bit is used to show the programming/erasing operation status of the flash memory. This bit will be set
to "1" when the flash memory program/erase cycle is completed. After flash memory program/erase cycle
is completed and the bit is still "0", programing/erasing the flash memory is not allowed. Only when this bit
is changed to "1", programming/erasing the flash memory is allowed. Writing "0" will clear this bit to "0" and
writing "1" to this bit will be ignored. When Automatic Algorithm (refer to Section C.4, Automatic Algorithm
Initiation Method) is completed, this bit will be set to "1". "1" is always read when read modify write (RWM)
is operated.
RDYINT
0
1
[bit 5] WE (Write Enable)
This bit is "write enable" for the flash memory. When this bit is set to "1", the flash memory can be
programed/erased right after the command sequence to FE~FF bank is issued. Furthermore, this bit is
used to start the command for programming/erasing the flash memory. It is recommended to always keep
this bit set to "0", so that the flash memory will not be programmed or erased accidentally.
WE
0
1
MB90580 Series
7
6
INTE
RDYINT
H
(R/W)
(R/W)
(0)
(0)
Interrupt enable when program/erase cycle is completed
Interrupt disable when program/erase cycle is completed
Programming/Erasing operation is on-going
Programming/Erasing operation is completed (interrupt request generated)
Disable programming/erasing flash memory
Enable programming/erasing flash memory
5
4
3
WE
RDY
Reserved
(R/W)
(W)
(W)
(X)
(0)
(0)
Interrupt Enable
Ready interrupt
Write Enable
Appendix C: The Flash Memory in the MB90F583
C.3 Flash Control Register (FMCS)
2
1
0
LPM1
Reserved
LPM0
(R/W)
(W)
(R/W)
(0)
(0)
(0)
Bit Number
FMCS
359
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