Shift Clock - Fujitsu F2MC-16LX Hardware Manual

18.3.1 Shift Clock

The shift clock supports two types of modes, internal shift clock mode and external
shift clock mode, that can be specified with the SMCS register. Change the modes
while the serial I/O is in the suspend state. To ensure the suspend state, read the
BUSY bit.
■ Internal Shift Clock Mode
By the output of the communication prescaler, a shift clock at duty cycle of 50% can be output at
the SCK pin as a synchronization timing output. Data is transferred by one bit per clock.
The transfer rate is calculated by the following expression.
Transfer rate (s) =
A is a division ratio, 2
Table 18.3-1 Set Value of SMD0 to SMD2 (Serial Shift Clock Mode Selection Bits) and Example of Setting
Shift Clock
SMD2 SMD1 SMD0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
div expresses the set value of the communication prescaler. For detailed information, see
"CHAPTER 16 COMMUNICATION PRESCALER REGISTER".
■ External Shift Clock Mode
In external shift clock mode, data is transferred by one bit per clock in synchronization with the
external shift clock input at SCK0 and SCK1 pins. The transfer rate can vary from DC to 1/(8
machine cycles). For example, when 1 machine cycle = 62.5 ns, the transfer rate can be up to
2 MHz.
Data can also be transferred on a per-instruction basis by making the following setting.
1. Select external shift clock mode and set 0 to the SCOE bit of the SMCS register.
2. Write 1 to the direction register of the port that shares the SCK0 and SCK1 pins to set the
port to output mode.
After setting as described above, when writing 1 and 0 to the data register of the port (PDR), the
value of the port output at SCK0 and SCK1 pins is captured as an external clock to operate a
transfer. Start the shift clock at H level.
Machine cycle of the internal clock (Hz)
1 2 4 5 6
, 2 , 2 , 2 , or 2
φ/div = 4 MHz φ/div = 2 MHz
2 Mbps 1 Mbps
1 Mbps 500 kbps
250 kbps 125 kbps
125 kbps 62.5 kbps
62.5 kbps 31.25 kbps
18.3 Operation of I/O Extended Serial Interface
A
, specified with the SMD bit of the SMCS register.
φ/div = 1 MHz
500 kbps
125 kbps
62.5 kbps
32.25 kbps
15.625 kbps
Calculation formula
1
(φ/div)/2
2
(φ/div)/2
4
(φ/div)/2
5
(φ/div)/ 2
6
(φ/div)/ 2
293