Shift Clock Modes - Fujitsu F2MC-16LX Hardware Manual

20.3.1 Shift Clock Modes

The shift clock has two modes, the internal shift clock mode and the external shift
clock mode. These two modes are specified by the setting of the SMCS. Change the
mode only when the serial I/O interface is not operating. This condition can be
determined by reading the BUSY bit.
I Internal shift clock mode
This mode operates based on an internal clock, and a shift clock with a duty ratio of 50% is
supplied via the SCK pin for synchronous timing output.
One bit of data is transferred for each clock. The data transfer speed can be calculated as
follows:
I External shift clock mode
In synchronization with an external shift clock supplied via the SCK pin, one bit of data is
transferred for each clock.
Data can be transferred at a speed up to 1/(8 machine cycles). For example, data can be
transferred at a speed of up to 2 MHz when one machine cycle is 62.5 µs.
Transfer for individual instructions can be achieved making the following settings:
• Select the external shift clock mode and set the SCOE bit of SMCS to "0".
• Write "1" to the direction register of the port that shares the SCK pin, then set the port to
output mode.
After making the above settings, write "1" and "0" to the data register (PDR) to obtain the value
of the port that is output to the SCK pin for supplying the external clock for data transfer. Start
the shift clock as soon as the "H"-level is input.
Note:
Writing to the SMCS and SDR during serial I/O operation is prohibited.
Transfer speed (S) =
Internal clock machine cycle (A)
"A" is the division ratio indicated by the SMD bit of SMCS.
÷ ÷
2
(φ div)/2, (φ div)/2 , (φ
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE
A
÷ ÷
4 5
div)/2 , (φ div)/2 , (φ
÷
6
div)/2
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