Altera cyclone V Technical Reference page 3102

21-6
Automatic RTS mode
Automatic RTS mode
Automatic RTS mode becomes active when the following conditions occur: †
• RTS (
MCR.RTS
• FIFO buffers are enabled (
When
rts_n
serial data until the receive FIFO buffer has available space (until it is completely empty). †
The selectable receive FIFO buffer threshold values are 1, ¼, ½, and 2 less than full. Because one additional
character may be transmitted to the UART after
transmitter block in the other UART), setting the threshold to 2 less than full allows maximum use of the
FIFO buffer with a margin of one character. †
Once the receive FIFO buffer is completely emptied by reading the receiver buffer register (
again becomes active (low), signaling the other UART to continue sending data.†
rts_n
Even when you set the correct
flow control is also disabled. When auto RTS is not implemented or disabled,
. In the Automatic RTS Timing diagram, the character T is received because
MCR.RTS
prior to the next character entering the sending UART transmitter. †
Figure 21-4: Automatic RTS Timing
rx_fifo_read
Automatic CTS mode
Automatic CTS mode becomes active when the following conditions occur: †
• AFCE (
• FIFO buffers are enabled (through FIFO buffer control register
When automatic CTS is enabled (active), the UART transmitter is disabled whenever the
becomes inactive (high). This prevents overflowing the FIFO buffer of the receiving UART. †
If the
cts_n
before the transmitter is disabled. While the transmitter is disabled, you can continue to write and even
overflow to the transmit FIFO buffer. †
Automatic CTS mode requires the following sequence:
1. The UART status register are read to verify that the transmit FIFO buffer is full (UART status register
USR.TFNF
2. The current FIFO buffer level is read via the transmit FIFO level (
3. Programmable THRE interrupt mode must be enabled to access the FIFO buffer full status from the
LSR. †
Altera Corporation
bit and
MCR.AFCE
FCR.FIFOE
is connected to the
cts_n
bits, if the FIFO buffers are disabled through
MCR
sin
start character T
rts_n
bit is set)
MCR.AFCE
input is not deactivated before the middle of the last stop bit, another character is transmitted
set to zero). †
bit are both set)
bit is set)
input pin of another UART device, the other UART stops sending
is inactive (due to data already having entered the
rts_n
stop start character T+1
1 2
FCR.FIFOE
is controlled solely by
rts_n
rts_n
stop
3 T
T+1
) bit
IIR_FCR.FIFOE
) register. †
TFL
cv_5v4
2016.10.28
),
RBR_THR_DLL
, automatic
is not detected
input
cts_n
UART Controller
Send Feedback