Altera cyclone V Technical Reference page 3208

cv_5v4
2016.10.28
31 30
15 14
cp_wdt_cnt_rst Fields
Bit
31:0
cp_wdt_cnt_rst
wdt_comp_param_1
This is a constant read-only register that contains encoded information about the component's parameter
settings.
Module Instance
l4wd0
l4wd1
Offset:
0xF4
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
Reserved
Watchdog Timer
Send Feedback
29 28 27 26
13 12 11 10
Name
The timeout period range is fixed. The range
increments by the power of 2 from 2 to the 16 to 2 to
the 31.
0xFFD02000
0xFFD03000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
cp_wdt_cnt_width
RO 0x10
13 12 11 10
cp_wdt_dflt_rpl
RO 0x0
Bit Fields
25 24 23 22
cp_wdt_cnt_rst
RO 0x7FFFFFFF
9 8 7 6
cp_wdt_cnt_rst
RO 0x7FFFFFFF
Description
Base Address
Bit Fields
25 24 23 22
cp_wdt_dflt_top_init
RO 0xF
9 8 7 6
cp_wdt_apb_ cp_ cp_
data_width wdt_ wdt_
pause use_
RO 0x2
fix_
RO
top
0x0
RO
0x1
wdt_comp_param_1
21 20 19 18
5 4 3 2
Access
Register Address
0xFFD020F4
0xFFD030F4
21 20 19 18
cp_wdt_dflt_top
RO 0xF
5 4 3 2
cp_ cp_ cp_ cp_
wdt_ wdt_ wdt_ wdt_
hc_ hc_ hc_ dual_
top rpl rmod top
RO RO RO RO
0x0 0x1 0x0 0x1
24-17
17 16
1 0
Reset
RO 0x7FFFF
FFF
17 16
1 0
cp_ cp_wdt_
wdt_ always_
dflt_ en
rmod
RO 0x0
RO
0x0
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