Altera cyclone V Technical Reference page 3090

20-72
ic_enable_status
31 30
15 14
ic_enable_status Fields
Bit
2
slv_rx_data_lost
Altera Corporation
29 28 27 26
13 12 11 10
Reserved
Name
This bit indicates if a Slave-Receiver operation has
been aborted with at least one data byte received from
an I2C transfer due to the setting of IC ENABLE from
1 to 0. When read as 1, i2c is deemed to have been
actively engaged in an aborted I2C transfer (with
matching address) and the data phase of the I2C
transfer has been entered, even though a data byte has
been responded with a NACK. NOTE: If the remote
I2C master terminates the transfer with a STOP
condition before the i2c has a chance to NACK a
transfer, and ic_enable has been set to 0, then this bit
is also set to 1. When read as 0, i2c is deemed to have
been disabled without being actively involved in the
data phase of a Slave-Receiver transfer. NOTE: The
CPU can safely read this bit when IC_EN (bit 0) is
read as 0.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
21 20 19 18
5 4 3 2
slv_
rx_
data_
lost
RO
0x0
Access
cv_5v4
2016.10.28
17 16
1 0
slv_ ic_en
disab
RO 0x0
led_
while
_busy
RO
0x0
Reset
RO 0x0
I2C Controller
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