Altera cyclone V Technical Reference page 3162

22-10
gpio_int_polarity
31 30
Reserved
15 14
gpio_inttype_level Fields
Bit
28:0
gpio_inttype_level
gpio_int_polarity
Controls the Polarity of Interrupts that can occur on inputs of Port A Data Register
Module Instance
gpio0
gpio1
gpio2
Offset:
0x3C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
29 28 27 26
13 12 11 10
Name
This field controls the type of interrupt that can occur
on the Port A Data Register. Note that only bits[26:0]
are implemented for
0x0
0x1
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
gpio_inttype_level
RW 0x0
9 8 7 6
gpio_inttype_level
RW 0x0
Description
.
gpio2
Value
Level-sensitive
Edge-sensitive
Base Address
0xFF708000
0xFF709000
0xFF70A000
21 20 19
5 4 3
Description
Register Address
0xFF70803C
0xFF70903C
0xFF70A03C
General-Purpose I/O Interface
cv_5v4
2016.10.28
18 17 16
2 1 0
Access Reset
RW 0x0
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