Altera cyclone V Technical Reference page 3148

21-52
cpr
dmasa Fields
Bit
0
dmasa
cpr
Describes various fixed hardware setups states.
Module Instance
uart0
uart1
Offset:
0xF4
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved dma_
extra
Altera Corporation
Name
This register is used to perform DMA software
acknowledge if a transfer needs to be terminated due
to an error condition. For example, if the DMA
disables the channel, then the uart should clear its
request. This will cause the Tx request, Tx single, Rx
request and Rx single signals to de-assert. Note that
this bit is 'self-clearing' and it is not necessary to clear
this bit.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
uart_ shado fifo_
add_ w stat
encod
RO RO RO
ed_
0x1 0x1 0x1
param
RO
0x1
Description
Base Address
0xFFC02000
0xFFC03000
Bit Fields
25 24 23 22
9 8 7 6
fifo_ addit sir_ sir_
acces ional lp_ mode
s _feat mode
RO
RO RO RO 0x0
0x1 0x1 0x0
Register Address
0xFFC020F4
0xFFC030F4
21 20 19 18
fifo_mode
RO 0x37
5 4 3 2
thre_ afce_ Reserved
mode mode
RO RO
0x1 0x1
cv_5v4
2016.10.28
Access Reset
WO 0x0
17 16
1 0
apbdatawidth
RO 0x2
UART Controller
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