Altera cyclone V Technical Reference page 3136

21-40
usr
RFW Fields
Bit
9
RFFE
8
rfpe
7:0
rfwd
usr
Status of FIFO Operations.
Module Instance
uart0
uart1
Offset:
0x7C
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
Name
These bits are only valid when FIFO access mode is
enabled (FAR[0] is set to one). When FIFO's are
enabled, this bit is used to write framing error
detection information to the receive FIFO. When
FIFO's are not enabled, this bit is used to write
framing error detection information to the RBR.
These bits are only valid when FIFO access mode is
enabled (FAR[0] is set to one). When FIFO's are
enabled, this bit is used to write parity error detection
information to the receive FIFO. When FIFO's are not
enabled, this bit is used to write parity error detection
information to the RBR.
These bits are only valid when FIFO access mode is
enabled (FAR[0] is set to one). When FIFO's are
enabled, the data that is written to the RFWD is
pushed into the receive FIFO. Each consecutive write
pushes the new data to the next write location in the
receive FIFO. When FIFO's are not enabled, the data
that is written to the RFWD is pushed into the RBR.
0xFFC02000
0xFFC03000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Base Address
0xFFC0207C
0xFFC0307C
2016.10.28
Access Reset
WO 0x0
WO 0x0
WO 0x0
Register Address
UART Controller
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cv_5v4