Altera cyclone V Technical Reference page 3118

21-22
fcr
Bit
5:4
tet
3
dmam
Altera Corporation
Name
This is used to select the empty threshold level at
which the THRE Interrupts will be generated when
the mode is active. It also determines when the uart
DMA transmit request signal uart_dma_tx_req_n
will be asserted when in certain modes of operation.
Value
0x0
0x1
0x2
0x3
This determines the DMA signalling mode used for
the uart_dma_tx_req_n and uart_dma_rx_req_n
output signals when additional DMA handshaking
signals are not selected. DMA mode 0 supports single
DMA data transfers at a time. In mode 0, the uart_
dma_tx_req_n signal goes active low under the
following conditions: -When the Transmitter Holding
Register is empty in non-FIFO mode. -When the
transmitter FIFO is empty in FIFO mode with
Programmable THRE interrupt mode disabled. -
When the transmitter FIFO is at or below the
programmed threshold with Programmable THRE
interrupt mode enabled. It goes inactive under the
following conditions -When a single character has
been written into the Transmitter Holding Register or
transmitter FIFO with Programmable THRE
interrupt mode disabled. -When the transmitter FIFO
is above the threshold with Programmable THRE
interrupt mode enabled. DMA mode 1 supports
multi-DMA data transfers, where multiple transfers
are made continuously until the receiver FIFO has
been emptied or the transmit FIFO has been filled. In
mode 1 the uart_dma_tx_req_n signal is asserted
under the following conditions: -When the
transmitter FIFO is empty with Programmable THRE
interrupt mode disabled. -When the transmitter FIFO
is at or below the programmed threshold with
Programmable THRE interrupt mode enabled.
Value
0x0
0x1
Description
Description
FIFO empty
Two characters in FIFO
FIFO 1/4 full
FIFO 1/2 full
Description
Single DMA Transfer Mode
Multiple DMA Transfer Mode
cv_5v4
2016.10.28
Access Reset
WO 0x0
WO 0x0
UART Controller
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