Altera cyclone V Technical Reference page 3204

cv_5v4
2016.10.28
wdt_crr Fields
Bit
7:0
wdt_crr
wdt_stat
Provides interrupt status
Module Instance
l4wd0
l4wd1
Offset:
0x10
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
wdt_stat Fields
Bit
0
wdt_stat
Watchdog Timer
Send Feedback
Name
This register is used to restart the watchdog counter.
As a safety feature to prevent accidental restarts, the
kick value of 0x76 must be written. A restart also
clears the watchdog interrupt.
Value
0x76
0xFFD02000
0xFFD03000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
Provides the interrupt status of the watchdog.
Value
0x1
0x0
Description
Description
Value to write to restart watchdog timer
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
Interrupt is active
Interrupt is inactive
wdt_stat
Access
Register Address
0xFFD02010
0xFFD03010
21 20 19 18
5 4 3 2
Access
24-13
Reset
WO 0x0
17 16
1 0
wdt_stat
RO 0x0
Reset
RO 0x0
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