Altera cyclone V Technical Reference page 3140

Hard processor system

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This is a shadow register for the RTS status (MCR[1]), this can be used to remove the burden of having to

performing a read modify write on the MCR.

Module Instance

Altera Corporation

This is a shadow register forthe Tx FIFO Reset bit

(FCR[2]). This can be used to remove the burden on

software having to store previously written FCR

values (which are pretty static) just to reset the

transmit FIFO.This resets the control portion of the

transmit FIFO and treats the FIFO as empty. This will

also de-assert the DMA Tx request and single signals.

This is a shadow register for the Rx FIFO Reset bit

(FCR[1]). This can be used to remove the burden on

software having to store previously written FCR

values (which are pretty static) just to reset the receive

FIFO. This resets the control portion of the receive

FIFO and treats the FIFO as empty. This will also de-

assert the DMA Rx request and single signals. Note

that this bit is 'self-clearing' and it is not necessary to

clear this bit.

This asynchronously resets the UART and synchro‐

nously removes the reset assertion.

No reset Tx FIFO

Reset Tx FIFO

No reset Rx FIFO

Reset Rx FIFO

No reset Uart

Base Address

UART Controller

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