Altera cyclone V Technical Reference page 3246

25-34
Message Handler Group Register Descriptions
MOIPX
on page 25-125
Reading this register allows the CPU to quickly detect if any of the interrupt pending bits in each of the
MOIPA, MOIPB, MOIPC, and MOIPD Interrupt Pending Registers are set.
MOIPA
on page 25-131
Interrupt pending bits for Message Objects 1 to 32. By reading the IntPnd bits, the CPU can check for
which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset
by the CPU via the IFx Message Interface Registers or set by the Message Handler after reception or after a
successful transmission of a frame. This will also affect the valid of IntID in the Interrupt Register.
MOIPB
on page 25-140
Interrupt pending bits for Message Objects 33 to 64. By reading the IntPnd bits, the CPU can check for
which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset
by the CPU via the IFx Message Interface Registers or set by the Message Handler after reception or after a
successful transmission of a frame. This will also affect the valid of IntID in the Interrupt Register.
MOIPC
on page 25-148
Interrupt pending bits for Message Objects 65 to 96. By reading the IntPnd bits, the CPU can check for
which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset
by the CPU via the IFx Message Interface Registers or set by the Message Handler after reception or after a
successful transmission of a frame. This will also affect the valid of IntID in the Interrupt Register.
MOIPD
on page 25-157
Interrupt pending bits for Message Objects 97 to 128. By reading the IntPnd bits, the CPU can check for
which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be set/reset
by the CPU via the IFx Message Interface Registers or set by the Message Handler after reception or after a
successful transmission of a frame. This will also affect the valid of IntID in the Interrupt Register.
MOVALX
Reading this register allows the CPU to quickly detect if any of the message valid bits in each of the
MOVALA, MOVALB, MOVALC, and MOVALD Message Valid Registers are set.
MOVALA
Message valid bits for Message Objects 1 to 32. By reading the MsgVal bits, the CPU can check for which
Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by the CPU via the
IFx Message Interface Registers.
MOVALB
Message valid bits for Message Objects 33 to 64. By reading the MsgVal bits, the CPU can check for which
Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by the CPU via the
IFx Message Interface Registers.
MOVALC
Message valid bits for Message Objects 65 to 96. By reading the MsgVal bits, the CPU can check for which
Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by the CPU via the
IFx Message Interface Registers.
MOVALD
Message valid bits for Message Objects 97 to 128. By reading the MsgVal bits, the CPU can check for
which Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by the CPU via
the IFx Message Interface Registers.
Altera Corporation
on page 25-166
on page 25-172
on page 25-180
on page 25-189
on page 25-197
cv_5v4
2016.10.28
CAN Controller
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