Altera cyclone V Technical Reference page 3237

cv_5v4
2016.10.28
Module Instance
can0
can1
Offset:
0x8
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
RP
RO 0x0
CERC Fields
Bit
15
RP
14:8
REC
7:0
TEC
CBT
This register is only writable if bits CCTRL.CCE and CCTRL.Init are set. The CAN bit time may be
programed in the range of [4 .. 25] time quanta. The CAN time quantum may be programmed in the range
of [1 .. 1024] CAN_CLK periods. For details see Application Note 001 "Configuration of Bit Timing". The
actual interpretation by the hardware of this value is such that one more than the value programmed here
is used. TSeg1 is the sum of Prop_Seg and Phase_Seg1. TSeg2 is Phase_Seg2. Therefore the length of the
CAN Controller
Send Feedback
0xFFC00000
0xFFC01000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
REC
RO 0x0
Name
Value
0x0
0x1
Actual state of the Receive Error Counter. Values
between 0 and 127.
Actual state of the Transmit Error Counter. Values
between 0 and 255.
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Description
The Receive Error Counter is below the error
passive level.
The Receive Error Counter has reached the
error passive level as defined in the CAN
Specification.
Register Address
0xFFC00008
0xFFC01008
21 20 19 18
5 4 3 2
TEC
RO 0x0
Access
25-25
CBT
17 16
1 0
Reset
RO 0x0
RO 0x0
RO 0x0
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