Internal Clock Mode (One-Shot Mode) - Fujitsu F2MC-16LX Hardware Manual

16.3.3 Internal Clock Mode (One-Shot Mode)

The counter is in synchronization with the internal count clock in this mode to count
down the 16-bit counter and generate an interrupt request to the CPU at counter
underflow. It also outputs a square wave from the TOT pin to indicate that counting is
in progress.
I Operation of Internal Clock mode (One-Shot Mode)
When count operation is allowed (TMCSR: CNTE=1) and the timer is started by the software
trigger bit (TMCSR: TRG) or external trigger, count operation will start. When both the count
enable bit and software trigger bit are set to "1", counting will start at the same time counting
becomes enabled. If the counter value causes an underflow (0000
stops at FFFF
bit for interrupt request (INTE) is set to "1", an interrupt request is generated.
The TOT pin outputs a square wave to indicate that counting is in progress.
❍ Software Trigger Operation
The counter will start as soon as the TRG bit of the timer control status registers (TMCSR) is set
to "1". Figure 16.3-7 "Count operation in one-shot mode (software trigger operation)" shows the
software trigger operation in one-shot mode.
Figure 16.3-7 Count operation in one-shot mode (software trigger operation)
Count clock
Counter
Data load signal
UF bit
CNTE bit
TRG bit
TOT pin
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
, and the underflow flag bit for interrupt requests (UF) is set to "1". If the enable
H
Reload
-1 0000 FFFF
data H H
Waiting for start trigger input
CHAPTER 16 16-BIT RELOAD TIMER
--> FFFF
H
Reload
-1 0000 FFFF
data H H
), the counter
H
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