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CHAPTER 4 BUS INTERFACE
4.6
Internal Clock Multiply Operation (Clock Doubler)
The MB91150 has a clock multiply circuit. The CPU internally operates at a frequency
obtained by multiplying the bus interface frequency by one or two. The bus interface
operates in synch with the CLK output pin regardless of the selected frequency.
If an external access request is made from the CPU, external access starts after the
CLK output goes high.
I Clock selection method
For the method of selecting multiply-by-one or multiply-by-two clock frequencies, see Section
3.11.4 "Gear Control Register (GCR)".
A selected clock can be changed even during chip operation. Bus operation is suspended while
clock selection is changed. When the system is reset, the clock obtained by multiplying the bus
interface frequency by 1 is assumed.
❍ Multiply-by-two clock
Figure 4.6-1 "Example of multiply-by-two clock timing" shows an example of multiply-by-two
clock timing under the following conditions:
•
Bus width: 16 bits
•
Access type: In words
Internal clock
Internal instruction address
Internal instruction data
CLK output
External address bus
External data bus
External RD
❍ Multiply-by-one clock
Figure 4.6-2 "Example of multiply-by-one clock timing" shows an example of multiply-by-one
clock timing under the following conditions:
•
Bus width: 16 bits
•
Access type: In words
144
Figure 4.6-1 Example of multiply-by-two clock timing
N
N
D
External access (instruction fetch)
N + 2
D + 2
N + 2
D + 2
D
N + 4
Pre-fetch
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