Table 3.7-7 Switching To Main Clock Mode Run State And Reset (Product In Single-Clock Configuration); Table 3.7-8 Switching To And From Standby Mode (Product In Single-Clock Configuration) - Fujitsu F2MC-8L Series Hardware Manual
8-bit microcontroller
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Also See for F2MC-8L Series:
- Hardware manual (131 pages) ,
- Application note (14 pages) ,
- Getting started (15 pages)
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CHAPTER 3 CPU
Switching to normal (RUN) state and reset
Table 3.7-7 Switching to Main clock Mode Run State and Reset (Product in Single-clock Configuration)
State transition
Transition to normal
(RUN) state after
power-on reset
Reset in RUN state
Switching to and from standby mode
Table 3.7-8 Switching to and from Standby Mode (Product in Single-clock Configuration)
State transition
Transition to sleep
mode
Wake-up from sleep
mode
Transition to stop
mode
Wake-up from stop
mode
STBC: Standby control register
Check:
When the CPU in the product without the power-on reset function wakes up from stop mode
by an external reset, the external reset must remain input until oscillation of the main clock
becomes stable.
90
Product with power-on reset function
(Figure 3.7-4)
[1]
End of main clock oscillation
stabilization delay time (Timebase
timer output)
[2]
Reset input canceled
[3]
External reset, software reset, or
watchdog reset
Product with power-on reset function
(Figure 3.7-4)
(1)
STBC : SLP="1"
(2)
Interrupt
(3)
External reset
(4)
STBC : STP= "1"
(5)
External interrupt
(6)
End of main clock oscillation
stabilization delay time (Timebase
timer output)
(7)
External reset
(8)
External reset (in oscillation
stabilization delay time)
Transition conditions
Product without power-on reset
function (Figure 3.7-5)
[1]
External reset input is required until
oscillation of the main clock
becomes stable.
[2]
Reset input canceled
[3]
External reset, software reset, or
watchdog reset
Transition conditions
Product without power-on reset
function (Figure 3.7-5)
(1)
STBC : SLP="1"
(2)
Interrupt
(3)
External reset
(4)
STBC : STP="1"
(5)
External interrupt
(6)
End of subclock oscillation
stabilization delay time (Timebase
timer output)
(7)
External reset
(8)
External reset (in oscillation
stabilization delay time)
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