State Transition Diagram 1 (Product With Power-On Reset Function In Dual-Clock Configuration); Figure 3.7-2 State Transition Diagram 1 (Product With Power-On Reset Function In Dual-Clock Configuration) - Fujitsu F2MC-8L Series Hardware Manual

3.7.6 State Transition Diagram 1 (Product with Power-on Reset
Function in Dual-clock Configuration)
This section provides the state transition diagram for the product with the power-on
reset function in the dual-clock configuration.

State Transition Diagram 1 (Product with Power-on Reset Function in Dual-clock Configuration)

Figure 3.7-2 State Transition Diagram 1 (Product with Power-on Reset Function in Dual-clock
<11>
Power on
Power-on reset
[1]
Oscillation
stabilization delay
reset state
(7)
Main-stop state
(5)
Main clock
(8)
oscillation
stabilization delay
[7]
<8>
subclock
oscillation
stabilization delay
<5>
<7>
Sub-stop state
[8]
<3>
3.7 Standby Modes (Low-power Consumption)
Configuration)
Reset state
[2] [3]
(4)
main-RUN state
(6)
[6]
[4]
main clock oscillation
stabilization delay
[5]
<6>
<1>
<4>
Sub-RUN state
<2>
<9> <10>
Watch state
(3)
Main clock mode
(1)
Main-sleep state
(2)
Subclock mode
Sub-RUN
Sub-sleep state
83