State Transition Of Counter Operation - Fujitsu MB90335 Series Hardware Manual

CHAPTER 14 16-BIT RELOAD TIMER
14.3 Movement of 16-bit Reload Timer
14.3.1

State Transition of Counter Operation

The state transition of the counter operation is shown.
■ State Transition of Counter Operation
Reset
WAIT state
TIN0 pin: only trigger input
TOT0 pin: output value
of 16-bit reload register
16-bit timer register:
Retained the value at stop
the value is undefined until loading
immediately after reset.
External trigger of TIN
Status transition by Hardware
Status transition by Register access
WAIT WAIT signal (internal signal)
TRG Software trigger bit (TMCSR0)
CNTE Timer counter enable bit (TMCSR0)
UF Timer interrupt request flag bit (TMCSR0)
RELD Reload operation enable bit (TMCSR0)
330
Figure 14.3-3 State Transition of Counter Operation
STOP state
TIN0 pin: input disabled
TOT0 pin: general-purpose I/O port
16-bit timer register:
Retained the value at stop
The value which is immediately
after reset is undefined.
CNTE = 0
CNTE = 1/TRG = 0
CNTE = 1, WAIT = 1
TRG = 1
(Software trigger)
LOAD
Load setting value of 16-bit reload
register to 16-bit timer register
FUJITSU MICROELECTRONICS LIMITED
CNTE = 0, WAIT = 1
CNTE = 1/TRG = 1
RUN state
TIN0 pin: function as input pin
UF = 1 &
TOT0 pin:
RELD = 0
(One-shot
mode)
16-bit timer register:
UF = 1 &
RELD = 1
(Reload mode)
CNTE = 1, WAIT = 0
MB90335 Series
CNTE = 0
CNTE = 1, WAIT = 0
of 16-bit reload timer
function as output pin
of 16-bit reload timer
Counter operation
TRG = 1
(Software trigger)
Load end
CM44-10137-6E