Counter Operation State - Fujitsu MB96300 series Hardware Manual

MB96300 Super Series Hardware Manual
15.6

Counter Operation State

The counter state is determined by the CNTE bit in the control status register and the
internal WAIT signal. Available states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE
= "1" and WAIT = "1" (WAIT state for trigger), and CNTE = "1" and WAIT = "0" (RUN state).
■ Counter operation states
Figure 15.6-1 "Counter state transitions" shows the transitions between each state.
Reset
CNTE=0
WAIT CNTE=1, WAIT=1
TIN pin: Only trigger input enabled
OUTE=0: General-purpose port
TOT pin:
OUTE=1: Initial value output
Counter: Retains the value while
counting stopped.
Value undefined after reset until
load.
External trigger from TIN
*1: Before using TIN pin, the corresponding bits of the DDR must be set to '0' and PIER register to '1'.
*2: In 'Gate Input mode': Counting can be influenced by TIN.
CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT
Figure 15.6-1 Counter state transitions
STOP CNTE=0, WAIT=1
TIN pin: Input disabled
OUTE=0: General-purpose port
TOT pin:
OUTE=1: Initial value output
Counter: Retains the value while
counting stopped.
Value undefined after reset.
CNTE=1
TRG=0
CNTE=1
TRG=1
*1
RELD • UF
TRG=1
LOAD CNTE=1, WAIT=0
Load contents of the reload
register to the counter.
State transitions by hardware
State transitions by external input
State transitions by register access
CNTE=0
RUN CNTE=1, WAIT=0
*1
TIN pin: Functions as TIN pin
OUTE=0: General-purpose port
TOT pin:
OUTE=1: Functions as TOT pin
*2
Counter: Running
TRG=1
RELD UF
External trigger from TIN
Load complete
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