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13.3.4 Counter status register 0/1 (CSR0/CSR1)
This section describes the configuration and explains the function of counter status
register 0/1 (CSR0/CSR1).
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Counter status register 0/1 (CSR0/CSR1)
The bit configuration of the counter status register 0/1 (CSR0/CSR1) is shown below.
Figure 13.3-5 Bit configuration of counter status register 0/1(CSR0/CSR1)
CSR0
ch.0 Address: 000072
CSR 1
ch.1 Address: 000074
Counter status register 0/1 (CSR0/CSR1) consists of bits that have the functions explained
below.
[bit7] CSTR (count start)
This bit is used to control the UDCR count start/stop operation.
CSTR
0
1
[bit6] CITE (compare interrupt output control)
This bit is used to control permit/prohibition of interrupt output to the CPU if CMPF is defined
(if a compare occurs).
CITE
0
1
[bit5] UDIE (overflow/underflow interrupt output control)
This bit is used to control the permit/prohibition of interrupt output to the CPU if OVFF/UDFF
is defined (if overflow/underflow occurs).
UDIE
0
1
bit
7
6
5
H
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
R/W
R/W
R/W R/W R/W
H
Count operation stop (initial value)
Count operation start
Permit/prohibit of compare interrupt output
Compare interrupt output prohibited (initial value)
Compare interrupt output permitted
Permit/prohibit of overflow/underflow interrupt output
Overflow/underflow interrupt output prohibited (initial value)
Overflow/underflow interrupt output permitted
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
4
3
2
1
R/W
R
Count start/stop operation
0
Initial value
00000000
B
R
271
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