Chip Select Enable Register (Cser) - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.2.7

Chip Select Enable Register (CSER)

The chip select enable register (CSER) set up the access permit of each chip select
area.
■ Configuration of the Chip Select Enable Register (CSER)
The chip select enable register (CSER: Chip Select Enable register) enables and disables each
chip select area.
Figure 4.2-7 shows the configuration of the chip select enable register (CSER).
Figure 4.2-7 Configuration of the Chip Select Enable Register (CSER)
Address 000680
000681
■ Functions of Bits in the Chip Select Enable Register (CSER)
The following explains the functions of the bits in the chip select enable register (CSER).
[bit31 to bit24] CSE7 to CSE0 (Chip Select Enable 0 to Chip Select Enable 7)
These bits are the chip select enable bits for CS0 to CS7.
The initial value is 00000001
When "1" is written, a chip select area operates according to the settings of ASR0 to ASR7,
ACR0 to ACR7, and AWR0 to AWR7.
Before setting this register, be sure to make all settings required for the corresponding chip
select areas. However, make sure to execute the power-on sequence by the PON bit in the
refresh control register (RCR) after enabling the chip select areas using the chip select area
enable register (CSER).
The power-on sequence is invalid to SDRAM/FCRAM connected to the area which has not
been enabled by the chip select area enable register (CSER).
Table 4.2-35 shows the function of chip select enable 0 to 7.
Table 4.2-35 Function of chip select enable 0 to 7
CSE7 to CSE0
172
bit 31 30 29
CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0 11111111
H
H
B
0
1
28 27 26 25
, which enables only the CS0 area.
Area control
Disable
Enable
24 Initial value
(INIT)
B
11111111 (RST)
B
Access
R/W