Clock Selection Register (Ckscr) - Fujitsu F2MC-16LX Hardware Manual

5.3

Clock Selection Register (CKSCR)

The clock selection register (CKSCR) sets and controls the CPU machine clock and
sets the oscillation stabilization time required at power-on or oscillation recovery.
■ Clock Selection Register (CKSCR)
Clock selection register
Address:
0000A1
Read/write
Initial value
[bit15] Reserved
Be sure to set this bit to "1".
[bit14] MCM
This bit indicates whether the main or the PLL clock is selected as the machine clock. When
this bit is "0", it indicates that the PLL clock is selected. When this bit is "1", it indicates that
the main clock is selected. When MCS is "0" and MCM is "1", the PLL clock is in the
oscillation stabilization wait state. The oscillation stabilization time for the PLL clock is fixed
13
to 2
[bit13, bit12] WS1, WS0
These bits set the oscillation stabilization time for the main clock required after the stop or
hardware standby mode is released. These bits are initialized to "11" by a power-on reset
but are not initialized by a reset caused by another reset cause. They are read/write bits.
Table 5.3-1 Clock Selection Register (bit13, bit12)
WS1
0
0
1
1
* : Approx. 65.54 ms (2
[bit11] Reserved
Be sure to set this bit to "1".
Figure 5.3-1 Clock Selection Register (CKSCR)
15 14 13
bit
Reserved MCM WS1
H
(-) (R) (R/W)
(1) (1) (1)
main clock cycles.
WS0
0 About 256 µs (2
1 About 2.05 ms (2
0 About 8.19 ms (2
1 About 32.77 ms (2
18
counts of source oscillation) at power-on.
5.3 Clock Selection Register (CKSCR)
12 11 10
WS0 MCS
Reserved
(R/W) (-) (R/W)
(1) (1) (1)
Oscillation stabilization time (OSC oscillation: 4 MHz)
10
OSC oscillation cycles)
13
OSC oscillation cycles)
15
OSC oscillation cycles)
17
OSC oscillation cycles) *
9
8
CS1 CS0 CKSCR
(R/W) (R/W)
(0) (0)
95