Figure 8-10: Tx Low Latency Buffered Mode: Use Model Tx_2G - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design
Figure 8-10
GearBox and 64B/66B Scrambler.
TXDATA (2,4,8B)
208
shows the buffered-mode flow through the TX bypassing the 10GBASE-R
TX_CLOCK_DIVIDER
TXUSRCLK
÷2
÷4
TXUSRCLK2
TXUSRCLK2 TXUSRCLK
TXOUTCLK1/
TXOUTCLK2
8B/10B
Encode
10GBASE-R
TXCHARISK
Encode (1)
ETC.
PCS
Note: (1) 64B/66B encoding/decoding is not supported.

Figure 8-10: TX Low Latency Buffered Mode: Use Model TX_2G

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TXCLK0_FORCE_PMACLK,
TX_CLOCK_DIVIDER
00
10 01 11
010 001
PCS
TXCLK
00
F
10
8x40 bit
Ring
T
Buffer
01
TXENC8B10BUSE,
TX_BUFFER_USE
TXENC64B66BUSE
011 000 1XX
PMA TXCLK0
PCS Dividers &
Clock Control
Phase Align
0001
0010
0000
10GBASE-R
Gearbox (1)
64B/66B
1100
Scrambler (1)
TXSCRAM64B66BUSE,
TXGEARBOX64B66BUSE,
TXDATA_SEL
ug076_ch8_21_071907
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
TXP
PISO
TXN
PMA