Rx Low Latency Buffer Bypass Mode; Overview; Clocking - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design

RX Low Latency Buffer Bypass Mode

Overview

For this mode, the RX buffer is bypassed and RXSYNC must be used to synchronize the
PCS RXCLK and PMA RXCLK0. The PCX RXCLK is used as the synchronization clock
source.

Clocking

In this mode, only the internal PCS dividers can be used for RXUSRCLK. As a result, this
mode is incompatible with channel bonding and 8-byte RX interface data path widths.
•
•
•
As shown in
Where RXRECCLK1 is used as the source for RXUSRCLK and RXUSRCLK2, the
asynchronous PMA clock dividers must be used. These dividers are not affected by the
phase alignment circuit. Therefore, the phase alignment circuit adjusts the phase only of
PMA RXCLK0, not of RXRECCLK1. This configuration requires attributes
RXCLKMODE[1] = 1, RXCLKMODE[4] = 0, and RXRECCLK1_USE_SYNC = FALSE.
Table 8-12: RX Use Models: Low-Latency Buffer Bypass Mode
RX_2A
Internal PCS
clock dividers
to derive
RX_2B
FALSE
RXUSRCLK
from
RXUSRCLK2
RX_2C
Notes:
1. All cases addressed assume a fabric width of 4 bytes. Refer to section
2. RXSYNC functionality must be used in order to sync the PCS/PMA clocks.
3. Because the internal PCS dividers are used, Parallel Loopback and Channel Bonding are not supported.
4. 64B/66B encoding/decoding is not supported.
224
If 4-byte mode is required, RX_CLOCK_DIVIDER = 11
If 2-byte mode is required, RX_CLOCK_DIVIDER = 01
If 1-byte mode is required, RX_CLOCK_DIVIDER = 10
Table 8-12, an external RXUSRCLK cannot be used in buffer-bypass mode.
No Bypass. Uses 8B/10B
Decode.
Decoding Bypass of 8B/10B
and 64B/66B Decode.
Full PCS Bypass, including
Comma Detection block.
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PORTS
0 1 1 0 0
REQ'D
0 1 0 0 0
0 0 0 0 0
"Clocking," page 224 for 2 byte or 1 byte fabric width.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
ATTRIBUTES
11 11
FALSE FALSE
10 11
01 11