Xilinx Virtex-4 RocketIO User Manual page 279

R
Table A-6: RocketIO RXUSRCLK2 Switching Characteristics (Continued)
Parameter
Clock to Out
T _CHBONDDONE
GT11CKO
T _CHBONDO
GT11CKO
T _RXBUFSTATUS
GT11CKO
T _RXCHARISCOMMA
GT11CKO
T _RXCHARISK
GT11CKO
T _RXCLKCORCNT
GT11CKO
T _RXCOMMADET
GT11CKO
T _RXCYCLELIMIT
GT11CKO
T _RXDATA
GT11CKO
T _RXDISPERR
GT11CKO
T _RXLOCK
GT11CKO
T _RXLOSSOFSYNC
GT11CKO
T _RXNOTINTABLE
GT11CKO
T _RXREALIGN
GT11CKO
T _RXRUNDISP
GT11CKO
T _RXSIGDET
GT11CKO
Clock
T _RX2
GPWH
T _RX2
GPWL
Notes:
1. These signals are asynchronous within the MGT. The software timing model treats these signals
synchronously with respect to RXUSRCLK2:
a. In a back-annotated timing simulation and in a static timing analysis, the user might see timing
violations if these signals are not synchronous to RXUSRCLK2.
b. The user can safely ignore these timing violations.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Timing Diagram and Timing Parameter Tables
Function
Status Output CHBONDDONE
Status Output CHBONDO
Status Output RXBUFSTATUS
Status Output RXCHARISCOMMA
Status Output RXCHARISK
Status Output RXCLKCORCNT
Status Output RXCOMMADET
Status Output RXCYCLELIMIT
Status Output RXDATA
Status Output RXDISPERR
Status Output RXLOCK
Status Output RXLOSSOFSYNC
Status Output RXNOTINTABLE
Status Output RXREALIGN
Status Output RXRUNDISP
Status Output RXSIGDET
Minimum Pulse
RXUSRCLK2
Width, High
Minimum Pulse
RXUSRCLK2
Width, Low
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