Xilinx Virtex-4 RocketIO User Manual page 25

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Table C-12: Dynamic Reconfiguration Port Memory Map: MGTA Address 72–76. . . . 304
Table C-13: Dynamic Reconfiguration Port Memory Map: MGTA Address 77–7B . . . 305
Table C-14: Dynamic Reconfiguration Port Memory Map: MGTA Address 7C–7F . . . 306
Table C-15: Dynamic Reconfiguration Port Memory Map: MGTB Address 40–44 . . . . 307
Table C-16: Dynamic Reconfiguration Port Memory Map: MGTB Address 45–49 . . . . 308
Table C-17: Dynamic Reconfiguration Port Memory Map: MGTB Address 4A–4E . . . 309
Table C-18: Dynamic Reconfiguration Port Memory Map: MGTB Address 4F–53 . . . . 310
Table C-19: Dynamic Reconfiguration Port Memory Map: MGTB Address 54–58 . . . . 311
Table C-20: Dynamic Reconfiguration Port Memory Map: MGTB Address 59–5D . . . 312
Table C-21: Dynamic Reconfiguration Port Memory Map: MGTB Address 5E–62. . . . 313
Table C-22: Dynamic Reconfiguration Port Memory Map: MGTB Address 63–67 . . . . 314
Table C-23: Dynamic Reconfiguration Port Memory Map: MGTB Address 68–6C . . . 315
Table C-24: Dynamic Reconfiguration Port Memory Map: MGTB Address 6D–71 . . . 316
Table C-25: Dynamic Reconfiguration Port Memory Map: MGTB Address 72–76 . . . . 317
Table C-26: Dynamic Reconfiguration Port Memory Map: MGTB Address 77–7B . . . 318
Table C-27: Dynamic Reconfiguration Port Memory Map: MGTB Address 7C–7F . . . 319
Table C-28: PLL Configuration Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Appendix D: Special Analog Functions
Table D-1: Register Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table D-2: Example RXSELDACTRAN and RXSELDACFIX Combinations . . . . . . . . . 321
Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO
Transceiver Design Migration
Table E-1: MGTs per Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Table E-2: Available Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Table E-3: Serial Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table E-4: Encoding Support and Clock Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table E-5: Power Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Table E-6: Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table E-7: CRC Transceiver Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table E-8: Loopback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table E-9: Status Bus Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Table E-10: Signal Optimization Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Appendix F: References
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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