Clocking - Xilinx Virtex-4 RocketIO User Manual

Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design Migration

Clocking

As with Virtex-II Pro/Virtex-II Pro X MGTs, there are several available clock inputs.
Table E-2
Table E-2: Available Clock Inputs
Clock Differential
Family
Names
BREFCLK
BREFCLK2
Virtex-II
Pro
REFCLK
REFCLK2
BREFCLK
Virtex-II
REFCLK
Pro X
REFCLK2
GREFCLK
Virtex-4 REFCLK1
REFCLK2
Notes:
1. Dynamic selection between the REFCLKs or the BREFCLKs; to switch from REFCLK to BREFCLK or vice versa requires
reconfiguration.
2. Reference clock switching is done via an attribute and the Dynamic Reconfiguration Port using the RXAPMACLKSEL,
RXBPMACLKSEL, and TXABPMACLKSEL attributes. These attributes are located at Dynamic Reconfiguration Port address 0x5D
on bits [13:12], [11:10], and [9:8] respectively.
3. BREFCLK should use dedicated GCLK I/O which decreases GCLK I/O resources for other logic (also two pins per clock).
4. There is only one BREFCLK on each side and cannot drive MGTs on the other side of the chip.
5. Depends on clock speed and implementation.
6. GREFCLK comes from the global clock tree which can come from any FPGA clock input, but should only be used for serial rates
under 1.0 Gb/s.
Clock selection has changed slightly over the past three generations of MGTs.
shows how the reference clocks are selected for each device.
refclk
0
1.5V
refclk2
1
REFCLKSEL
0
brefclk
2.5V
brefclk2
1
Virtex-II Pro
326
shows the clocks for each family and the serial speeds they are available for.
Dedicated
(Internal) Routes Speeds (Gb/s)
Yes
Yes
Yes Yes
recommended
recommended
Yes Yes
Yes Yes
Yes Yes
REFCLKBSEL
REF_CLK_V_SEL
refclk
refclk2
0
refclk_out
REFCLKSEL
to PCS and PMA
1
brefclkp
brefclkn
Virtex-II Pro X
Figure E-1: Reference Clock Selection for Each Device
www.xilinx.com
Max Serial Dynamic
Switching
(1)
3.125 Yes
(1)
3.125 Yes
(1)
2.5 Yes
(1)
2.5 Yes
6.25 Yes
Not
Yes
Not
Yes
(2)
1.0 Yes
(2)
6.5 Yes
(2)
6.5 Yes
0
1.5V
1
0
refclk_out
to PCS and PMA
1
2.5V
Package Inputs per
Input Device (No. of
Voltage Package Pins)
(3)
2.5 8
(3)
2.5 8
(3)
2.5 8
(3)
2.5 8
(5) (4)
2.5/3.3 4
(3)
2.5 8
(3)
2.5 8
TBD (6)
TBD 8
TBD 8
Figure E-1
PMACLKSEL
refclk1
refclk_out
refclk2
to PCS and PMA
grefclk
Note: All Virtex-4 clocks are differential.
Virtex-4
ug076_apD_01_013105
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Clocks
per
Device
(3)
2
(3)
2
(3)
2
(3)
2
(4)
2
(3)
2
(3)
2
(6)
4
4