Xilinx Virtex-4 RocketIO User Manual page 281

R
Table A-7: RocketIO TXUSRCLK Switching Characteristics (Continued)
Clock to Out
Clock
Notes:
1. These signals are asynchronous within the MGT. The software timing model treats these signals
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Parameter
T _TXBUFERR
GT11CKO
T _TXCALFAIL
GT11CKO
T _TXCYCLELIMIT
GT11CKO
T _TXKERR
GT11CKO
T _TXLOCK
GT11CKO
T _TXRUNDISP
GT11CKO
T _TX
GPWH
T _TX
GPWL
T _TX2
GPWH
T _TX2
GPWL
synchronously with respect to TXUSRCLK2:
a. In a back-annotated timing simulation and in a static timing analysis, the user might see timing
violations if these signals are not synchronous to TXUSRCLK2.
b. The user can safely ignore these timing violations.
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Timing Diagram and Timing Parameter Tables
Function
Status Output TXBUFERR
Status Output TXCALFAIL
Status Output TXCYCLELIMIT
Status Output TXKERR
Status Output TXLOCK
Status Output TXRUNDISP
Minimum Pulse
TXUSRCLK
Width, High
Minimum Pulse
TXUSRCLK
Width, Low
Minimum Pulse
TXUSRCLK2
Width, High
Minimum Pulse
TXUSRCLK2
Width, Low
Signal
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