Chan_Bond_Seq_1_Mask, Chan_Bond_Seq_2_Mask; Chan_Bond_Seq_Len, Chan_Bond_Seq_*_* Attributes; Disable Channel Bonding; Setting Chan_Bond_Limit - Xilinx Virtex-4 RocketIO User Manual

Multi-gigabit transceiver
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Chapter 3: PCS Digital Design Considerations

CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_MASK,

CHAN_BOND_SEQ_LEN, CHAN_BOND_SEQ_*_* Attributes

These attributes operate exactly the same as their clock correction counterparts. See
Table 3-14
bits, and
CHAN_BOND_SEQ_*_MASK.

Disable Channel Bonding

To disable channel bonding, set CHAN_BOND_MODE to OFF.

Setting CHAN_BOND_LIMIT

CHAN_BOND_LIMIT should be set to the largest possible value less than one-half the
minimum distance between channel bonding sequences. This allows the GT11 to correct
the largest possible lane skews without the possibility of slaves finding two copies of the
channel bonding character while attempting to bond. For example, if a standard or
application specifies a skew of ±8 (16 absolute) 8-bit or 10-bit symbols, then
CHAN_BOND_LIMIT must be set to 7.

Implementation Guidelines

The transceiver CHBONDI/CHBONDO buses are daisy-chained together as shown in
Figure
Whether a slave is a 1-hop or 2-hop slave, internal logic causes the data driven on the
CHBONDO bus from the master to be recognized by the slaves at the same time and must
be deterministic. Therefore, it is important that the interconnect of CHBONDO-to-
CHBONDI not contain any pipeline stages. The data must transfer from CHBONDO to
CHBONDI in one clock cycle.
The transceiver requires one place-and-route restriction when channel bonding is
implemented. Because of the delay limitations on the CHBONDO to CHBONDI ports,
linking of the master to a Slave_1_Hop must run either in the X or Y direction, but not both.
130
IDLE
IDLE
CCCB_ABITRATOR_DISABLE = FALSE
IDLE
CC
68 Bytes + CHAN_BOND_LIMIT minimum
distance between clock correction (CC)
and channel bond (CB) sequences.
Figure 3-19: Effects of CCCB_ARBITRATOR_DISABLE = TRUE
for clock correction bit definitions analogous to the CHAN_BOND_SEQ_*_*
Table 3-16
and
Table 3-17
3-20.
www.xilinx.com
No gap needed between clock
correction and channel bonding
sequences. Clock correction
takes priority.
CC
CB
12 bytes between
channel bond (CB)
sequences.
CB
IDLE
CCCB_ABITRATOR_DISABLE = TRUE
for mask information analogous to
Virtex-4 RocketIO MGT User Guide
IDLE
IDLE
CB
ug076_ch3_15_062806
UG076 (v4.1) November 2, 2008
R

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