Restrictions On Low Latency Buffer Bypass Modes - Xilinx Virtex-4 RocketIO User Manual

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Restrictions on Low Latency Buffer Bypass Modes

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Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
RX phase alignment should not be initiated until all involved RX PLLs are locked.
Refer to section "Resets" in Chapter 2
settings (for example, RXFDET_LCK_SEL and RXLOOPFILT), the required RXLOCK-
to-RXSYNC interval (TLOCK_to_SYNC) can vary greatly, from a few RXUSRCLK2
cycles to several thousand RXUSRCLK2 cycles.
a. It is recommended that RXSYNC be asserted after RXLOCK has remained High
for at least 12,000 RXUSRCLK2 cycles. This requirement is already met if the user
waits for 16K (16 x 1024) REFCLK cycles to make sure that RXLOCK is asserted for
that time. Refer to section
b. This TLOCK_to_SYNC interval can be reduced when using a different
RXFDET_LCK_SEL setting.
The RXSYNC port must remain asserted for the entire phase alignment process.
a. It is recommended that RXSYNC should be asserted for least 64 synchronization
clock cycles. Since RXUSRCLK is the clock source for the PCS RXCLK domain, this
would be 64 RXUSRCLK cycles.
b. If multiple RXSYNC pulses are necessary, it is also recommended that they be
spaced at least four synchronization clock (RXUSRCLK) cycles apart.
c. If RXSYNC is left asserted, it acts as an enable, such that if the PMA RXCLK0 edge
is detected prior to the reference clock, and RXSYNC is High, a clock adjustment is
executed, dropping one high-speed serial clock (and the associated data). Bringing
RXSYNC Low causes the circuit to stay locked in its current position; therefore,
after alignment is complete, RXSYNC should be brought Low
Finally, the PCS reset, RXRESET, must be asserted on all MGTs involved in the phase
alignment to reset all the MGTs.
a. The interval between RXSYNC deasserting and RXRESET asserting
(TSYNC_to_RST) can be as small as zero RXUSRCLK2 cycles.
b. The RXRESET pulse (TRST) normally should be synchronized to the RXUSRCLK2
domain and should remain asserted for at least three RXUSRCLK cycles. This
must be translated to the appropriate number of RXUSRCLK2 cycles based on the
fabric width of 1, 2, or 4 bytes. Refer to
Clock correction is not supported because the RX ring buffer is bypassed. (This can be
mitigated by using RXRECCLK1/RXRECCLK2 to derive the clocks for RXUSRCLK
and RXUSRCLK2.)
Channel bonding is not supported because the RX ring buffer is bypassed. (This can be
implemented in the fabric if required.)
Fabric width of 8 bytes is not supported.
Fabric widths of 2 bytes and 1 byte can be supported only by the internal PCS dividers
controlled by the RX_CLOCK_DIVIDER and TX_CLOCK_DIVIDER attributes.
External RXUSRCLK/TXUSRCLK connections cannot be used.
Parallel loopback for 2-byte and 1-byte fabric width is not supported in low-latency
buffer bypass modes because the internal PCS dividers are used in this mode. PCS
Loopback is only supported in 4-byte fabric width in RX low-latency mode.
64B/66B is not supported because the low-latency buffer bypass modes are
incompatible with the gearbox and blocksync functionality.
In PCS bypass mode, external data width of 1 byte and 2 bytes are not supported.
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Restrictions on Low Latency Buffer Bypass Modes
for more details Depending on the RX PLL
.
"Resets" in Chapter 2 for more details.
"Resets" in Chapter 2 for more details.
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