Xilinx Virtex-4 RocketIO User Manual page 195

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Table 8-2: Latency through Various Transmitter Components/Processes
Notes:
1. See
2. Fabric interface has delays in both clock domains. Clock ratios are:
3. The Latency of the 8B/10B Encoder is 2 TXUSRCLKs when the data is taken directly into the PMA
4. 28 UI is the latency through the PISO for the first bit transmitted. For the entire word, it is 28 UI + 32 UI
5. These delays include a registered data mux, which accounts for one clock of delay.
6. 64B/66B encoding/decoding is not supported.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Transmit Blocks 1 Byte
4 TXUSRCLK2 +
(2)
Fabric Interface
1 TXUSRCLK
8B/10B
(6)
64B/66B
(5)
Bypass
TX Buffer
Scrambling
& Gearbox
(5)
Bypass
(5)
PMA Interface
PMA Register
PISO
Chapter 5, "Cyclic Redundancy Check (CRC)"
a. 1-byte mode USR2:USR ratio = 4:1
b. 2-byte mode USR2:USR ratio = 2:1
c. 4-byte mode USR2:USR ratio = 1:1
d. 8-byte mode USR2:USR ratio = 1:2
interface, TXDATA_SEL = 10, else it is 3 TXUSRCLKs.
or 40 UI, depending on internal datapath width.
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2 Byte 4 Byte
2 TXUSRCLK2 + 1 TXUSRCLK2 +
1 TXUSRCLK 1 TXUSRCLK
(3)
2 or 3 TXUSRCLK
3 TXUSRCLK
1 TXUSRCLK
1
3 / TXUSRCLK / PCS TXCLK
2
2 PCS TXCLK
1 PCS TXCLK
1 PCS TXCLK
1 PMA TXCLK0
(4)
28 UI – 68 UI
for more information on CRC Latency.
PCS Data Path Latency
(1)
8 Byte
1 TXUSRCLK2 +
2 TXUSRCLK
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