Basic Architecture And Capabilities - Xilinx Virtex-4 RocketIO User Manual

R
RocketIO Transceiver Overview

Basic Architecture and Capabilities

The RocketIO™ Multi-Gigabit Transceiver (MGT) block diagram is illustrated in
Figure 1-1, page
transceiver modules, as shown in
Table 1-1: Number of MGT Cores per Device Type
Notes:
1. Number of MGTs depends on the package.
The transceiver module is designed to operate at any serial bit rate in the range of
622 Mb/s to 6.5 Gb/s per channel, including the specific bit rates used by the
communications standards listed in
Table 1-2: Communications Standards Supported by the MGT
Notes:
1. One channel is considered to be one transceiver.
2. See
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
36. Depending on the device, a Virtex®-4 FPGA has between 8 and 24
Device
XC4VFX20
XC4VFX40
XC4VFX60
XC4VFX100
XC4VFX140
Mode
SONET OC-12
Fibre Channel (1, 2, 4X)
Gigabit Ethernet
Infiniband
PCI Express
Serial RapidIO
Serial ATA
XAUI (10 Gigabit Ethernet)
10 Gigabit Fibre Channel (4 x 3.1875G)
(2)
Aurora Protocol
www.xilinx.com/aurora
www.xilinx.com
Table 1-1.
RocketIO MGT Cores
8
12
(1)
12 or 16
20
24
Table 1-2.
(1)
Channels
1
1
1
1/4/12
1/2/4/8/16
1/4
1
4
4
1/2/3/4...
for details.
Chapter 1
(Lanes) I/O Bit Rate (Gb/s)
0.622
1.06/2.12/4.25
1.25
2.5
2.5
1.25/2.5/3.125
1.5/3
3.125
3.1875
0.622 – 6.5
35