Pcs Data Path Latency - Xilinx Virtex-4 RocketIO User Manual

Chapter 8: Low-Latency Design

PCS Data Path Latency

The relationship between USRCLK and USRCLK2 (both TX and RX) depends on several
factors, including the fabric interface width and the serial standard used. Another
important timing consideration is the clock delay for data to pass through the entire MGT.
Table 8-1
depend on the external parallel data bus width (shown) and the phase relationship
between the different clocks, adding a small uncertainty factor to this table.
Table 8-1: Latency through Various Receiver Components/Processes
Notes:
1. See
2. Linear equalization does not affect the receiver latency.
3. These delays include a registered data mux, which accounts for one clock of delay.
4. Bypass is when RXDEC8B10BUSE and RXDEC64B66BUSE are both deasserted.
5. Bypassed buffer accounts for one registered data mux = 1 RXUSRCLK, but must be equal to 1 RXCLK0
6. Fabric interface has delays in both clock domains. Clock ratios are:
7. 64B/66B encoding/decoding is not supported.
194
and Table 8-2 show approximate clock cycles for the main PCS blocks. The cycles
Receive Blocks
RX SERDES
(3)
PMA_PCS Interface
CommaDET/Align
Bypass
8B/10B
(7)
64B/66B
(3)
Bypass
No Clock
Correction
Clock Correction
Min/Max Used
Decode
(3)
Bypass
(6)
Fabric Interface
Chapter 5, "Cyclic Redundancy Check (CRC)"
to bypass buffer. (Only works reliably if RX low-latency buffer bypass mode is implemented.)
a. 1-byte mode USRCLK2:USRCLK ratio = 4:1
b. 2-byte mode USRCLK2:USRCLK ratio = 2:1
c. 4-byte mode USRCLK2:USRCLK ratio = 1:1
d. 8-byte mode USRCLK2:USRCLK ratio = 1:2
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1 Byte 2 Byte
62 UI or 80 UI
2 PCS RXCLK
3 PCS RXCLK
1 PCS RXCLK
2 PCS RXCLK
2 PCS RXCLK
1 PCS RXCLK
3 PCS RXCLK + RXUSRCLK (phase diff) + 8 RXUSRCLK Latency +
1 RXUSRCLK
(3 PCS RXCLK + 1 RXUSRCLK + CLK_COR_MIN_LAT/4) < latency
< (3 PCS RXCLK + 1 RXUSRCLK + CLK_COR_MAX_LAT/4)
2 RXUSRCLK
1 RXUSRCLK
1 RXUSRCLK + 1 RXUSRCLK +
4 RXUSRCLK2 2 RXUSRCLK2
for more information on CRC Latency.
(1,2)
4 Byte 8 Byte
1 RXUSRCLK + 2 RXUSRCLK +
1 RXUSRCLK2 1 RXUSRCLK2
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
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