Xilinx Virtex-4 RocketIO User Manual page 300

Appendix C: Dynamic Reconfiguration Port
Table C-8: Dynamic Reconfiguration Port Memory Map: MGTA Address 5E–62
Bit
(1)
5E Def
15 0
14 0
13 0
RESERVED
[5:0]
12 0
11 0
10 0
9 PMA_BIT_SLIP 0
8 X
RXASYNCDIVIDE
[1:0]
7 X
6 X
5 X
4 X
RXCLKMODE
[5:0]
3 X
2 X
1 X
0 RXLB 0
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
300
5F Def 60
0 RXBYPASS_CAL
1
RXFDET_HYS_CAL
0
[2:0]
0
0
RXFDET_LCK_CAL
0
[2:0]
0
0
RXEQ
RXFDET_HYS_SEL
[63:48]
0
[2:0]
0
0
RXFDET_LCK_SEL
0
[2:0]
0
0 RXVCO_CTRL_ENABLE
0
RXCYCLE_LIMIT_SEL
[1:0]
0
Table C-28, page 320 for details
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Address
Def
(2)
N/A
MCOMMA_32B_VALUE
(2)
0
(2)
0
61 Def 62
RESERVED
N/A
[15:0] [15:0]
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Def
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0