Xilinx Virtex-4 RocketIO User Manual page 218

Chapter 8: Low-Latency Design
Table 8-10: Worst-Case Skew Estimates
Data Rate UI (ps)
622 Mb/s 1608
1.25 Gb/s 800
2.5 Gb/s 400
3.125 Gb/s 320
6.5 Gb/s 153.85
Notes:
1. 1-byte mode is not supported for 3.125 Gb/s data rate, and 1-byte and 2-byte modes are not supported for 6.5 Gb/s data rate,
because fabric interface speed is limited to 250 MHz.
218
Internal
TXUSRCLK Source
Data Path
Internal PCS Dividers
External TXUSRCLK
32
Internal PCS Dividers
External TXUSRCLK
Internal PCS Dividers
External TXUSRCLK
40
Internal PCS Dividers
External TXUSRCLK
Internal PCS Dividers
External TXUSRCLK
32
Internal PCS Dividers
External TXUSRCLK
Internal PCS Dividers
External TXUSRCLK
40
Internal PCS Dividers
External TXUSRCLK
Internal PCS Dividers
External TXUSRCLK
40
Internal PCS Dividers
External TXUSRCLK
Internal PCS Dividers
40
External TXUSRCLK
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Synchronization Clock
Fabric Data
PCS TXCLK
Width
UI (ns)
4 2.3048 3.71
4
2 18.3048 29.43
1 26.3048 42.29
2, 1
4 2.6125 2.09
4
2 22.6125 18.09
1 32.6125 26.09
2, 1
4 3.225 1.29
4
2 19.225 7.69
1 27.225 10.89
2, 1
4 3.225 1.29
4
2 23.225 9.29
1 33.225 13.29
2, 1
4 3.5313 1.13
4
2 23.5313 7.53
2
4 5.185 0.8
4
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
GREFCLK
UI (ns)
2.1057 3.39
2.1057 3.39
18.1057 29.11
26.1057 41.97
2.1057 3.39
2.2125 1.77
2.2125 1.77
22.2125 17.77
32.2125 25.77
2.2125 1.77
2.425 0.97
2.425 0.97
18.425 7.37
26.425 10.57
2.425 0.97
2.425 0.97
2.425 0.97
22.425 8.97
32.425 12.97
2.425 0.97
2.5313 0.81
2.5313 0.81
22.5313 7.21
2.5313 0.81
3.105 0.48
3.105 0.48