Xilinx Virtex-4 RocketIO User Manual page 43

R
Table 1-5: RocketIO MGT PMA Ports (Continued)
Port
Special Signals
RXSIGDET
RXSYNC
TXENOOB
TXSYNC
Table 1-6: RocketIO MGT PCS Ports
Port
Channel Bonding
CHBONDI
CHBONDO
ENCHANSYNC
(1)
64B/66B
RXBLOCKSYNC64B66BUSE
(1)
RXDEC64B66BUSE
RXDESCRAM64B66BUSE
(1)
RXIGNOREBTF
(1)
RXLOSSOFSYNC
(1)
TXENC64B66BUSE
TXGEARBOX64B66BUSE
TXSCRAM64B66BUSE
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
I/O Port Size
O 1
I 1
I 1
I 1
I/O Port Size
I 5
O 5
I 1
(1)
I 1
I 1
(1)
I 1
I 1
O 2
I 1
(1)
I 1
(1)
I 1
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When set to logic 1, indicates that an out-of-band (OOB) signal
has been detected. When proper differential signal input is being
received, RXSIGDET is logic 0. See
Design Considerations" for details.
Controls the RX PMA phase aligner used for clock phase
alignment in reduced latency modes. See
Domains and Data Paths" in Chapter
Enables the transmitter to send electric idle signals on the
TXN/TXP pins when set to a logic 1. See
Analog Design Considerations"
Controls the TX PMA phase aligner used for clock phase
alignment in reduced latency modes and to reduce transmitter
output skew across MGTs for channel bonded applications. See
Chapter 3, "PCS Digital Design Considerations"
The channel bonding control that is used only by "slaves"
which are driven by a transceiver's CHBONDO port.
Channel bonding control that passes channel bonding and
clock correction control to other transceivers.
Control from the fabric to the transceiver which enables the
transceiver to perform channel bonding.
Reserved. Tie to logic 0.
Reserved. Tie to logic 0.
Reserved. Tie to logic 0.
Reserved. Tie to logic 0.
Reserved.
Reserved. Tie to logic 0.
Reserved. Tie to logic 0.
Reserved. Tie to logic 0.
Available Ports
Definition
Chapter 4, "PMA Analog
"PMA/PCS Clocking
2.
Chapter 4, "PMA
for details.
for details.
Definition
43