Xilinx Virtex-4 RocketIO User Manual page 89

R
Refer to the following points in conjunction with this figure:
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Below are the steps describing the flow chart in
1.
2.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
The flow chart uses TXUSRCLK and TXUSRCLK2 as reference to the wait time for
each state. Do not use TXUSRCLK and TXUSRCLK2 as the clock source for this block;
these clocks might not be present during some states. Use a free-running clock (for
example, the system's clock) and make sure the wait time for each state equals the
specified number of TXUSRCLK and TXUSRCLK2 cycles.
It is assumed that the frequency on TXUSRCLK is slower than the one on
TXUSRCLK2. If TXUSRCLK2 is slower, use that clock as reference to the wait time for
each state. An exception to this requirement is the wait time between assertions of
TXLOCK and TXSYNC signals, from TX_WAIT_LOCK to TX_SYNC states; use the
specified TXUSRCLK2 in this step.
See Figure 8-11, "TXSYNC Timing," page 214
cycles and the 64 synchronization clock cycles specified in this block.
tx_usrclk_stable is a status signal from the user's application that is asserted High
when both TXUSRCLK and TXUSRCLK2 clocks are stable. For example, if a DCM is
used to generate both the TXUSRCLK and TXUSRCLK2 clocks, then the DCM
LOCKED signal can be used here.
tx_align_err is a status from the user's application that is asserted High when there are
errors on the transmission of data as a result of the TX phase alignment not being
successful after TXSYNC is applied.
tx_sync_cnt is a counter from the user's application that is incremented every time
both the tx_align_err and TXLOCK signals are asserted. It is reset when the block
cycles back to the TX_PMA_RESET state.
In synchronous systems like the GPON application where
RXRECCLK1/RXRECCLK2 is used for the TX PLL, the TX_SYSTEM_RESET state
should stall until there is a stable RXLOCK signal from the RX PLL (RXLOCK == 1 for
16K [16 x 1024] REFCLK cycles). The condition in going from TX_SYSTEM_RESET to
TX_PMA_RESET needs to be modified to:
♦
Analog CDR Mode:
!system_reset && (RXLOCK == 1 for 16K [16 x 1024] REFCLK cycles)
♦
Digital CDR Mode:
!system_reset && RXLOCK == 1
See "RX Reset Sequence Background," page 100
cycles requirement.
TX_SYSTEM_RESET: Upon TX system reset on this block, go to the TX_PMA_RESET
state.
TXPMARESET == 0
TXRESET == 0
TXSYNC == 0
TX_PMA_RESET: Assert TXPMARESET for three TXUSRCLK cycles.
TXPMARESET == 1
TXRESET == X
TXSYNC == 0
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regarding the 12,000 TXUSRCLK2
for information on the 16K REFCLK
Figure 2-16:
Resets
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