Figure 6-6: Optimizing Filtering For An Mgt Column - Xilinx Virtex-4 RocketIO User Manual

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number of power pins that must be filtered. Several conditions require that the power
supply be filtered:
•
•
Figure 6-6
GT11CLK_MGT_inst1
Note:
1 Gb/s, normal clock inputs can be used with appropriate termination circuitry.
Case A spreads the MGTs that are used among the column. In this case, the SYNCLK passes
through MGT_TILE_2 to clock MGT_inst_2 at the top.
Case B (recommended) condenses the MGTs that are used around the utilized
GT11CLK_MGT_inst. This case has no unused tiles with the clock passing through them,
and this ultimately reduces the number of required filtering networks.
Table 6-1
for each case shown in
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
The GT11CLK_MGT of a tile is used.
The SYNCLK1 or SYNCLK2 pass through a tile to reach another tile.
shows two scenarios of MGT utilization for an XC4VFX60-FF1152 device.
Case A
MGT_Tile_3
MGT_inst_2
A
B
Not Used_4
MGT_Tile_2
Not Used_3
A
B
Not Used_2
MGT_Tile_1
MGT_inst_1
A
B
MGT_inst_0
MGT_Tile_0
Not Used_1
A
B
Not Used_0

Figure 6-6: Optimizing Filtering for an MGT Column

Figure 6-6 assumes that the dedicated GT11CLK_MGT is used. For serial rates under
and Table 6-2 show which AVCCAUXRXB and AVCCAUXMGT must be filtered
Figure
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GT11CLK_MGT_inst1
6-6.
Physical Requirements
Case B
MGT_Tile_3
Not Used_4
A
B
Not Used_3
MGT_Tile_2
Not Used_2
A
B
MGT_inst_2
MGT_Tile_1
MGT_inst_1
A
B
MGT_inst_0
MGT_Tile_0
Not Used_1
A
B
Not Used_0
ug076_ch6_04_022305
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