Xilinx Virtex-4 RocketIO User Manual page 305

R
Table C-13: Dynamic Reconfiguration Port Memory Map: MGTA Address 77–7B
Bit
77
15
14
CHAN_BOND_SEQ_1_MASK
[3:0]
13
12
11
10
9
8
7
CHAN_BOND_SEQ_1_4
6
[10:0]
5
4
3
2
1
0
CHAN_BOND_SEQ_1_3[10]
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
3. Although there is an open-loop divider for each MGT, both attributes map into MGTA locations in the DRP Memory Map:
TXOUTDIV2SEL (for MGTB) Reg 0x6A [14:11]
TXOUTDIV2SEL (for MGTA) Reg 0x7A [15:12]
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Def 78 Def
RESERVED
N/A
VCODAC_INIT
(2)
[9:0]
N/A
0
SLOWDOWN_CAL
(2)
[1:0]
0
(2)
BYPASS_FDET
N/A
LOOPCAL_WAIT
(2)
[1:0]
Table C-28, page 320 for details.
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Address
79 Def
TXOUTDIV2SEL
TXPLLNDIVSEL
PCOMMA_32B_VALUE
N/A
[31:16]
Memory Map
(1)
7A Def 7B
X
X
(3)
[3:0]
X
X
X
X
[3:0]
X
X
RESERVED
[15:0]
0
RESERVED
[1:0]
0
X
X
TXLOOPFILT
(2)
[3:0]
X
X
0
RESERVED
[1:0]
0
Def
N/A
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