Xilinx Virtex-4 RocketIO User Manual page 337

R
L
Latency and Timing 157
32-Bit Example 159
158
64-Bit Example
133
LOOPBACK
134
Loopback Modes (figure)
Loopback Modes (table) 134
239
Losses, PCB
240
Loss tangent
240
Permittivity
Resistive, from skin effect
Low-Latency Design 191
192
Data Paths
192
PCS Clocking Domains
194
PCS Data Path Latency
Ports and Attributes see Ports, Low-
Latency and Attributes, Low-La-
tency
M
Max Data Rate Example (32-Bit) (figure)
159
Max Data Rate Example (64-Bit) (figure)
158
Memory Map 294
MGT
Basic Architecture and Capabilities
35
Block Diagram 36
Clock Descriptions (table)
35
Overview
MGT Clock Descriptions (table)
MGT Column Clocking (figure)
MGT Features 27
MGT Power Control Descriptions (table)
151
MGT Protocol Settings (table)
MGT Receive Clocking 70
MGT Receive Clocking (figure)
MGT Timing Relative to Clock Edge (fig-
ure) 275
MGT Transmit Clocking 68
MGT Transmit Clocking (figure)
30
MGT, term definition
Microstrip Edge-Coupled Differential
Pair (figure) 178
252
Microstrip/Stripline Bends
327
Migration Differences
179
Model Considerations
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
N
Number of MGT Cores per Device Type
35
(table)
O
Obstacle Route Geography (figure)
Out-of-Band (OOB) Signals
Output Swing and Emphasis
240
P
PCB design guidelines
BGA escape, example
Channel budgeting
HM-Zd conn. dsgn., example
SMT blocking cap. dsgn., example
267
SMT conn. dsgn., examples
PCB Level Design
Guidelines and Examples
Methodology
PCB Materials and Traces
Transitions see Transitions, PCB
PCS Digital Design Considerations
PCS Primitive Ports (table)
Physical Requirements
PMA Analog Design Considerations
PMA Attribute
Bus Ports (table)
271
Programming Bus
PMA Configurations
271
PMA Power Control Description (table)
62
152
PMA Primitive Ports (table)
PMA Receive Clocks
PMA Receiver Power Control Description
37
(table) 151
PMA Transmit Clocks
70
Ports
CHBONDI
CHBONDO
COMBUSIN
68
COMBUSOUT
DADDR
47
DCLK
DEN 47
DI 47
47
DO
47
DRDY
47
DWE
ENCHANSYNC
www.xilinx.com
178
149
143
257
261
258
264
262 263
,
235 239 245 257
, , ,
257
235
239
101
43
163
139
293
293
75
41
69 70
,
68
43
43
47
47
47
43
45
ENMCOMMAALIGN
ENPCOMMAALIGN 45
GREFCLK 47
47
LOOPBACK
47
POWERDOWN
47
REFCLK1
REFCLK2 47
RXBLOCKSYNC64B66BUSE
46
RXBUFERR
41
RXCALFAIL
RXCHARISCOMMA 44
RXCHARISK 44 113
,
41
RXCLKSTABLE
45
RXCOMMADET
45
RXCOMMADETUSE
RXCRCCLK 40
RXCRCDATAVALID 40
40
RXCRCDATAWIDTH
40
RXCRCIN
40
RXCRCINIT
RXCRCINTCLK 40
RXCRCOUT 40
40
RXCRCPD
40
RXCRCRESET
41
RXCYCLELIMIT
RXDATA 45
45
RXDATAWIDTH
43
RXDEC64B66BUSE
44
RXDEC8B10BUSE
RXDESCRAM64B66BUSE 43
RXDISPERR 44 113
,
43
RXIGNOREBTF
45
RXINTDATAWIDTH
42
RXLOCK
RXLOSSOFSYNC 43
RXMCLK 42
41
RXN
44 114
RXNOTINTABLE
,
41
RXP
RXPCSHCLKOUT 42
42
RXPMARESET
41
RXPOLARITY
45
RXREALIGN
RXRECCLK1 42
RXRECCLK2 42
46
RXRESET
44 113
RXRUNDISP
,
43
RXSIGDET
RXSLIDE 45
RXSTATUS 46
46
RXUSRCLK
46
RXUSRCLK2
43
337