64-Bit Example - Xilinx Virtex-4 RocketIO User Manual

Chapter 5: Cyclic Redundancy Check (CRC)
After wakeup of the CRC, CRCRESET has to be asserted for at least two CRCCLK clock
cycles. When CRCRESET is deasserted, the user should wait two CRCCLK clock cycles
before starting data transfer. CRCRESET is asynchronous.
When CRCRESET is asserted, it kills the pipeline immediately. CRCOUT and the internal
initialization value are set to all zeroes. Hence, the user has to assert CRCINIT with
CRCDATAVALID to obtain the correct CRCOUT.

64-Bit Example

Notice that valid CRCOUT data only occurs at the 64-bit word boundary clocked by
CRCINTCLK, although internally all the CRC values at the 32-bit boundary are clocked by
CRCCLK.
CRCINTCLK
xx
CRCIN [63:0]
CRCINIT
CRCDATAVALID
CRCCLK
Internal CRCIN [31:0]
Internal CRCOUT [31:0]
CRCOUT[31:0]
158
xx (2) (4) (6) (8)
x x x x 1 2 3 4 5 6 7
x x x x x 1 2 3 4 5 6 7 8
xx xx xx xx 1
C
Initial CRC
Figure 5-3: Max Data Rate Example (64-Bit)
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(-8) (-6) (-4) (-2)
8 -9 -8 -7 -6 -5 -4 -3 -2 -1 n
-9 -8 -7 -6 -5 -4 -3 -2 -1
3 5 -7
C C C
Internal valid CRC values
(n) xx xx xx xx
x x x x x x
n
x x
C
-5 -3 -1 n xx
C C C C
Output CRC
ug076_ch5_04_080805
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R