Xilinx Virtex-4 RocketIO User Manual page 297

R
Table C-5: Dynamic Reconfiguration Port Memory Map: MGTA Address 4F–53
Bit
4F Def
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
RXEQ TXCRCINITVAL
[31:16]
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Notes:
1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
50 Def 51
RESERVED
N/A
[15:0] [15:0]
www.xilinx.com
Address
Def 52 Def
RESERVED
[5:0]
N/A N/A
COMMA_10B_MASK
[9:0]
Memory Map
53 Def
RXFDCAL_CLOCK_DIVIDE
[1:0]
TXFDCAL_CLOCK_DIVIDE
[1:0]
N/A
RXBY_32
RESERVED
ENABLE_DCDR
SAMPLE_8X
DCDR_FILTER
(1)
[2:0]
RXUSRDIVISOR
N/A
[4:0]
0
1
0
297