Xilinx Virtex-4 RocketIO User Manual page 312

Appendix C: Dynamic Reconfiguration Port
Table C-20: Dynamic Reconfiguration Port Memory Map: MGTB Address 59–5D
Bit
(1)
59 Def
15 X
14 X
RXOUTDIV2SEL
(3)
[3:0]
13 X
12 X
11 X
10 X
RXPLLNDIVSEL
[3:0]
9 X
8 X
7 0
RESERVED
[1:0]
6 0
5 X
4 X
RXLOOPFILT
(2)
[3:0]
3 X
2 X
1 RXDIGRX 0
0 RESERVED 0
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
3. This register value must equal the register value at address 0x49, bit[14:11] on MGTB. The attribute RXOUTDIV2SEL sets both registers upon configuration, but
must be written to separately using the DRP.
4. Applies to MGTA only.
5. Applies to MGTB only.
312
5A Def
RXRECCLK1_USE_SYNC
TXOUTCLK1_USE_SYNC
TXCLK0_FORCE_PMACLK
RXCLK0_FORCE_PMACLK
TX_CLOCK_DIVIDER
RX_CLOCK_DIVIDER
RESERVED
N/A
[15:0]
TXCRCENABLE
RESERVED
TXCRCINVERTGEN
TXCRCCLOCKDOUBLE
RXCRCENABLE
RESERVED
RXCRCINVERTGEN
RXCRCCLOCKDOUBLE
Table C-28, page 320 for details.
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Address
5B Def 5C
[1:0]
[1:0]
RXEQ
N/A
[63:48]
Def 5D
0
RESERVED
[1:0]
1
0
RXPMACLKSEL
(4)
[1:0]
0
0
RXPMACLKSEL
(5)
[1:0]
0
0
TXABPMACLKSEL
[1:0]
0
0
0
0
0
RESERVED
[7:0]
0
0
0
0
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
R
Def
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0